Techniques for protecting integrated circuits from large, undesirable current and voltage signals due to electrostatic discharges, over-voltage conditions and the like (hereinafter "ESD events") are well known. For example, each input/output (I/O) pad of an integrated circuit typically is provided with a diode coupled between the I/O pad and a reference terminal (e.g., ground) and a diode coupled between the I/O pad and a voltage terminal (e.g., V.sub.dd). In response to an ESD event that generates a large positive voltage on the I/O pad, the diode coupled between the I/O pad and the voltage terminal conducts and dissipates the large positive voltage from the I/O pad to the voltage terminal. However, the diode coupled between the reference terminal and the I/O pad is reverse biased and does not conduct in response to the positive voltage on the I/O pad (i.e., no direct path is generated between the I/O pad and the reference terminal).
Because no direct path exists between the I/O pad and the reference terminal for dissipating large positive voltages present on the I/O pad, the only path for dissipating such voltages from the I/O pad to the reference terminal is a path from the I/O pad to the voltage terminal (via the diode coupled therebetween), and from the voltage terminal to the reference terminal via the IC chip capacitance. The effectiveness/efficiency of this indirect voltage dissipation path depends sensitively on the IC chip's capacitance and the resistance of the voltage terminal bus. When either the IC chip's capacitance is small or the voltage terminal bus is highly resistive, poor ESD protection is afforded by the path from the I/O pad to the voltage terminal and from the voltage terminal to the reference terminal. Accordingly, a need exists for an improved method and apparatus for providing electrostatic discharge protection for integrated circuits, particularly for ESD events that generate large positive voltages on the I/O pads of IC chips.